DIGITALLY-ASSISTED ANALOG CIRCUITS FOR HYBRID PIXEL X-RAY DETECTORS

The dissertation describes the theoretical studies and experimental tests of the multichannel readout circuits for hybrid X-ray detectors, addressing aspects of the design of integrated circuits which contain both analog circuitry as well as digital logic integrated on the same silicon substrate. Combining more and more functionality inside a pixel is a trend observed in nowadays readout integrated circuits. However, integration of several blocks of diverse functionality in each readout channel and implementation of inter-pixel communication impose new challenges in the process of simulation, design, implementation and verification of the integrated mixed-mode systems.

Scientific problems addressed by this dissertation aim at improving design process of mixed-mode readout integrated circuits, in particular, with the algorithms dealing with charge sharing implemented inside a chip. To achieve this goal, the basic concepts of X-ray detector systems and their limitations are studied. Then, the algorithms implemented in mixed-mode integrated circuits for dealing with charge sharing and selected solutions from the literature are discussed. The C8P1 algorithm, developed by the ASIC group from the AGH University of Science and Technology, is a subject of detailed conceptual analyses and simulations as a known solution to the charge sharing problem. The simulation approach to this algorithm and implementation of realistic models, including practical aspects, for example, non-ideal comparators, noise or analog parameters spread is presented. The influence of analog parameters spread on the detector registration is analysed. The simulations are conducted in static and dynamic modes.

The target of the experimental part of the thesis is to confirm the conclusions obtained through the simulations. Firstly, the architecture and design aspects of the multichannel readout integrated circuit named Chase Jr. chip with the C8P1 algorithm are presented. The operation and configuration of the chip with an emphasis on analog path reconfiguration for the purpose of testing and trimming is revealed. The dedicated measurement environment implemented for the Chase Jr. tests and the practical realisation of the testing procedures for the Chase Jr. chip are described. The measurement results for the Chase Jr. chip bonded to a silicon sensor are shown. Three types of experiments are conducted: the preliminary integrated circuit tests without X-ray radiation performed for calibration purposes, the experiments using an X-ray tube and the experiments using specialised synchrotron source, used mainly for the assessment of the algorithm dealing with charge sharing in this work. The experiments include the tests of signal reconstruction in the case of charge sharing, the tests of registration at pixel borders, the tests of influence of correction on the C8P1 algorithm and the high count rate tests.

The results of the simulations and measurements lead to the conclusions that the integrated circuit with the C8P1 algorithm switched on allows reconstruction of the total photon energy from fractional signals in the case of charge sharing between two or four pixels, and thus, the photons can be detected even at pixel borders, where the standard approach fails. This proves that the charge sharing effect occurring in hybrid pixel detectors can be compensated by mixed analog-digital circuits implemented inside the readout electronics using inter-pixel communication strategies. However, increasing pixel-to-pixel gain spread, DC offset spread and noise, result in the significant degradation of the detection efficiency in the C8P1 mode. Therefore, there is a need for dedicated correction circuits to minimise the analog parameters spread between channels and assure the proper operation of the detector. The results of the tests of the Chase Jr. chip prove in practice, that it is possible to overcome technology limitations regarding analog parameters spread of the multichannel integrated circuits for hybrid pixel detectors with inter-pixel communication, using digitally assisted correction blocks.

• Autoreferat w języku polskim Autoreferat (PL),

• Spis treści pracy doktorskiej: Digitally-Assisted Analog Circuits for Hybrid Pixel X-Ray Detectors ,

Pełna treść rozprawy jest dostępna w bibliotece Akademii Górniczo-Hutniczej.

• A. Krzyżanowska, P. Gryboś, R. Szczygieł, and P. Maj, “Testing multistage gain and offset trimming in a single photon counting IC with a charge sharing elimination algorithm,” J. Instrum., vol. 10, no. 12, pp. C12003–C12003, 2015.

• A. Drozd, R. Szczygiel, P. Maj, T. Satlawa, and P. Grybos, “Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips,” J. Instrum., vol. 9, no. 12, pp. C12046–C12046, 2014.

• P. Maj, (A.Drozd), et al., “Measurements of matching and noise performance of a prototype readout chip in 40 nm CMOS process for hybrid pixel detectors,” IEEE Trans. Nucl. Sci., vol. 62, no. 1, pp. 359–367, 2015.

• A. Krzyżanowska, G. Deptuch, P. Maj, P. Gryboś, and R. Szczygieł, “Simulation approach to charge sharing compensation algorithms with experimental cross-check,” J. Instrum., vol. 12, no. 3, pp. C03071–C03071, 2017.

• P. Maj, A. Drozd, R. Szczygiel, and P. Gryboś, “FPGA simulations of charge sharing effect compensation algorithms for implementation in deep sub-micron technologies,” Proc. - UKSim 15th Int. Conf. Comput. Model. Simulation, UKSim 2013, pp. 780–786, 2013.
• P. Maj, (A. Drozd) et al., “A pixel readout chip in 40 nm CMOS process for high count rate imaging systems with minimization of charge sharing effects,” IEEE Nucl. Sci. Symp. Conf. Rec., 2013.
• T. Satlawa, A. Drozd, and P. Kmon, “Design of the ultrafast LVDS I/O interface in 40 nm CMOS process,” Proc. 21st Int. Conf. Mix. Des. Integr. Circuits Syst. Mix. 2014, pp. 200–204, 2014.
• A. Krzyzanowska, P. Maj, P. Grybos, R. Szczygiel, and A. Koziol, “Methodology of automation process of wafer tests,” Proc. 22nd Int. Conf. Mix. Des. Integr. Circuits Syst. Mix. 2015, pp. 530–533, 2015.
• A. Krzyzanowska, G. W. Deptuch, P. Maj, P. Grybos, and R. Szczygiel, “Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam,” IEEE Trans. Nucl. Sci., vol. 64, no. 9, pp. 2561–2568, Sep. 2017.
• P. Grybos, A. Drozd, R. Kleczek, P. Maj, and R. Szczygiel, “Digitally assisted low noise and fast signal processing charge sensitive amplifier for single photon counting systems,” in 2015 IEEE International Conference on Industrial Technology (ICIT), 2015, pp. 1445–1450.

• Chiara Guazzoni, prof. Politecnico di Milano Recenzja nr 1 (EN), Recenzja nr 2 (PL)
• dr hab. inż. Jacek Marczewski, prof. ITE Recenzja nr 1 (EN), Recenzja nr 2 (PL)