Spis treści

Zaproszenie na obronę pracy doktorskiej

zapraszają na
publiczą dyskusję nad rozprawą doktorską

mgr inż. Aleksandry Krzyżanowskiej
Termin: 28 września 2018 roku o godz. 10:00
Miejsce: Sala 4, al. Mickiewicza 30, pawilon B-1, parter
PROMOTOR: dr hab. inż. Grzegorz Deptuch, Akademia Górniczo-Hutnicza im. St. Staszica w Krakowie
PROMOTOR POMOCNICZY: dr hab. inż. Piotr Maj, Akademia Górniczo-Hutnicza im. St. Staszica w Krakowie
RECENZENCI: Chiara Guazzoni, prof. Politecnico di Milano
dr hab. inż. Jacek Marczewski, prof. ITE



The dissertation describes the theoretical studies and experimental tests of the multichannel readout circuits for hybrid X-ray detectors, addressing aspects of the design of integrated circuits which contain both analog circuitry as well as digital logic integrated on the same silicon substrate. Combining more and more functionality inside a pixel is a trend observed in nowadays readout integrated circuits. However, integration of several blocks of diverse functionality in each readout channel and implementation of inter-pixel communication impose new challenges in the process of simulation, design, implementation and verification of the integrated mixed-mode systems.

Scientific problems addressed by this dissertation aim at improving design process of mixed-mode readout integrated circuits, in particular, with the algorithms dealing with charge sharing implemented inside a chip. To achieve this goal, the basic concepts of X-ray detector systems and their limitations are studied. Then, the algorithms implemented in mixed-mode integrated circuits for dealing with charge sharing and selected solutions from the literature are discussed. The C8P1 algorithm, developed by the ASIC group from the AGH University of Science and Technology, is a subject of detailed conceptual analyses and simulations as a known solution to the charge sharing problem. The simulation approach to this algorithm and implementation of realistic models, including practical aspects, for example, non-ideal comparators, noise or analog parameters spread is presented. The influence of analog parameters spread on the detector registration is analysed. The simulations are conducted in static and dynamic modes.

The target of the experimental part of the thesis is to confirm the conclusions obtained through the simulations. Firstly, the architecture and design aspects of the multichannel readout integrated circuit named Chase Jr. chip with the C8P1 algorithm are presented. The operation and configuration of the chip with an emphasis on analog path reconfiguration for the purpose of testing and trimming is revealed. The dedicated measurement environment implemented for the Chase Jr. tests and the practical realisation of the testing procedures for the Chase Jr. chip are described. The measurement results for the Chase Jr. chip bonded to a silicon sensor are shown. Three types of experiments are conducted: the preliminary integrated circuit tests without X-ray radiation performed for calibration purposes, the experiments using an X-ray tube and the experiments using specialised synchrotron source, used mainly for the assessment of the algorithm dealing with charge sharing in this work. The experiments include the tests of signal reconstruction in the case of charge sharing, the tests of registration at pixel borders, the tests of influence of correction on the C8P1 algorithm and the high count rate tests.

The results of the simulations and measurements lead to the conclusions that the integrated circuit with the C8P1 algorithm switched on allows reconstruction of the total photon energy from fractional signals in the case of charge sharing between two or four pixels, and thus, the photons can be detected even at pixel borders, where the standard approach fails. This proves that the charge sharing effect occurring in hybrid pixel detectors can be compensated by mixed analog-digital circuits implemented inside the readout electronics using inter-pixel communication strategies. However, increasing pixel-to-pixel gain spread, DC offset spread and noise, result in the significant degradation of the detection efficiency in the C8P1 mode. Therefore, there is a need for dedicated correction circuits to minimise the analog parameters spread between channels and assure the proper operation of the detector. The results of the tests of the Chase Jr. chip prove in practice, that it is possible to overcome technology limitations regarding analog parameters spread of the multichannel integrated circuits for hybrid pixel detectors with inter-pixel communication, using digitally assisted correction blocks.

Praca doktorska

Pełna treść rozprawy jest dostępna w bibliotece Akademii Górniczo-Hutniczej.

Wybrane publikacje autora rozprawy